Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - serial verilog

Search list

[VHDL-FPGA-Verilog] parameter_uart_rx

Description: 串口接收模块，可以通过parameter，参数化配置传输速率、传输位宽和校验。采用Verilog语音编程实现。使用者根据串口的要求配置好参数，并根据缓冲的大小配置FIFO就可以使用。对帧错误（停止位不为高），检验错误和读FIFO超时（FIFO满的情况下，有新的数据到）等现象进行了检查。(UART serial receiver module, through parameter, configuration parameters of the transmission rate, Data width and parity. Using Verilog. The user configured the parameters according to the serial port and configured FIFO according to the size of the buffer. The frame error (stop bit is not high), check errors, and read FIFO timeout (when FIFO is full,and new data come) and so on are examined.)
Platform: | Size: 4096 | Author: 老工程师 | Hits:

[VHDL-FPGA-Verilog] RS232

Description: 基于quartusii的用verilog编写的rs232串口程序(QuartusII based on Verilog prepared by the RS232 serial procedures)
Platform: | Size: 948224 | Author: qiaodecheng | Hits:

[VHDL-FPGA-Verilog] chuankou

Description: 此文件是一个串口verilog程序，一次传输一个字节，使用quartus编写(This is a program that is written in Verilog language ,It is a Serial program ,You can transfer and return a byte data.)
Platform: | Size: 7168 | Author: wangshuo9242 | Hits:

[Other] LCD-104

Description: serial flash memeory interface with verilog
Platform: | Size: 239616 | Author: eng_mohamed12 | Hits:

[VHDL-FPGA-Verilog] uart_test

Description: verilog写的串口发送机，虽然简单，但是注释写的比较清楚，适合新学习FPGA的同学作参考(Serial transmitter written in Verilog)
Platform: | Size: 3135488 | Author: ppp鹏鹏鹏 | Hits:

[VHDL-FPGA-Verilog] project2

Description: 基于Verilog在quartus平台上搭建的串口通信模型，适用于初学者。本实验所用RXD的波特率为9600，TXD波特率为9600×16，1位起始位，8位数据位（ASCII码），1位停止位，无奇偶校检位。接收数据时，至少连续采样8个周期都是“0”后，才认定为起始位，之后每隔16个周期取一次数据。(Verilog based on the quartus platform to build a serial communication model, suitable for beginners.)
Platform: | Size: 116736 | Author: 锂离子 | Hits:

[VHDL-FPGA-Verilog] No.201710061347=UART_Verilog

Description: 1.硬件平台： FPGA； 2.编程语言： Verilog； 3.串口通信RS232的Verilog实现版本；(1. hardware platform: FPGA; 2. programming language: Verilog; The Verilog implementation version of 3. serial port communication RS232;)
Platform: | Size: 56320 | Author: 记忆工人2017 | Hits:

[VHDL-FPGA-Verilog] 新建文本文档

Description: Verilog编写的按键代码，采用异步串口传输协议，并带有偶校验。(Verilog's key code, asynchronous serial port transmission protocol, and with even check.)
Platform: | Size: 1024 | Author: engineerlj | Hits:

[VHDL-FPGA-Verilog] 07_uart_test

Description: 黑金FPGA开发板实现串口Uart通信的verilog代码(Serial Uart communication)
Platform: | Size: 390144 | Author: 啊啊啊阿波 | Hits:

[VHDL-FPGA-Verilog] experiment_4_uart_communication

Description: 这是一个uart串口通信的代码，是基于ise运行的verilog语言，可以实现上位机和开发板的通信以及开发板显示数据并返回累加和的功能。( This is a serial code for uart communication is based on running ise verilog language, you can achieve PC and development board communications, and development boards to display the data and return the cumulative sum function.)
Platform: | Size: 2985984 | Author: michael lee | Hits:

[Other] Tx

Description: 利用verilog实现串口发送，每次按键一次发送一次数据，按键模块进行了消抖处理(Using Verilog to realize serial port sending. Each button sends one data at a time, and the key module performs buffeting processing.)
Platform: | Size: 4088832 | Author: liyd | Hits:
« 1 2 ... 29 30 31 32 33 34»

CodeBus www.codebus.net